SystemVerilog for Design (Hardcover)
 
作者: Simon Davidmann 
書城編號: 1054783


售價: $2500.00

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出版社: Springer
出版日期: 2006/07/20
尺寸: 231x155x30mm
重量: 0.79 kg
ISBN: 9780387333991

商品簡介


In its updated second edition, this book has been extensively revised on a chapter by chapter basis to include the many text and example updates needed to reflect changes adopted between the first edition of the book and the finalization of the new standard. The book accurately reflects the syntax and semantic changes to the SystemVerilog language, making it an essential reference for systems professionals who need the latest version information. In addition, the second edition features a new chapter that explains the SystemVerilog "packages", a new appendix that summarizes the synthesis guidelines presented throughout the book, and all of the code examples have been updated to the final syntax and rerun using the latest version of the Synopsys, Mentor, and Cadance tools.

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